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19-3645; Rev 0; 4/05
KIT ATION EVALU ILABLE AVA
Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs
Features
Excellent Dynamic Performance 69.9dB SNR at 5.3MHz 96dBc SFDR at 5.3MHz 95dB Channel Isolation Ultra-Low Power 96mW per Channel (Normal Operation) Serial LVDS Outputs Pin-Selectable LVDS/SLVS (Scalable Low-Voltage Signal) Mode LVDS Outputs Support Up to 30 Inches FR-4 Backplane Connections Test Mode for Digital Signal Integrity Fully Differential Analog Inputs Wide Differential Input Voltage Range (1.4VP-P) On-Chip 1.24V Precision Bandgap Reference Clock Duty-Cycle Equalizer Compact, 100-Pin TQFP Package with Exposed Paddle Evaluation Kit Available (Order MAX1437EVKIT)
General Description
The MAX1437 octal, 12-bit analog-to-digital converter (ADC) features fully differential inputs, a pipelined architecture, and digital error correction incorporating a fully differential signal path. This ADC is optimized for low-power and high-dynamic performance in medical imaging instrumentation and digital communications applications. The MAX1437 operates from a 1.8V single supply and consumes only 768mW (96mW per channel) while delivering a 69.9dB (typ) signal-to-noise ratio (SNR) at a 5.3MHz input frequency. In addition to low operating power, the MAX1437 features a power-down mode for idle periods. An internal 1.24V precision bandgap reference sets the full-scale range of the ADC. A flexible reference structure allows the use of an external reference for applications requiring increased accuracy or a different input voltage range. The reference architecture is optimized for low noise. A single-ended clock controls the data-conversion process. An internal duty-cycle equalizer compensates for wide variations in clock duty cycle. An on-chip PLL generates the high-speed serial low-voltage differential signal (LVDS) clock. The MAX1437 has self-aligned serial LVDS outputs for data, clock, and frame-alignment signals. The output data is presented in two's complement or binary format. The MAX1437 offers a maximum sample rate of 50Msps. See the Pin-Compatible Versions table below for higherand lower-speed versions. This device is available in a small, 14mm x 14mm x 1mm, 100-pin TQFP package with exposed paddle and is specified for the extended industrial (-40C to +85C) temperature range.
MAX1437
Ordering Information
PART MAX1437ECQ TEMP RANGE -40C to +85C PIN-PACKAGE 100 TQFP-EP* (14mm x 14mm x 1mm)
*EP = Exposed paddle.
Applications
Ultrasound and Medical Imaging Instrumentation Multichannel Communications
PART MAX1434 MAX1436 MAX1438**
Pin-Compatible Versions
SAMPLING RATE (Msps) 50 40 65 RESOLUTION (BITS) 10 12 12
**Future product--contact factory for availability.
Pin Configuration appears at the end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs MAX1437
ABSOLUTE MAXIMUM RATINGS
AVDD to GND.........................................................-0.3V to +2.0V CVDD to GND ........................................................-0.3V to +3.6V OVDD to GND ........................................................-0.3V to +2.0V IN_P, IN_N to GND...................................-0.3V to (AVDD + 0.3V) CLK to GND .............................................-0.3V to (CVDD + 0.3V) OUT_P, OUT_N, FRAME_, CLKOUT_ to GND................................-0.3V to (OVDD + 0.3V) DT, SLVS/LVDS, LVDSTEST, PLL_, T/B, REFIO, REFADJ, CMOUT to GND .......-0.3V to (AVDD + 0.3V) Continuous Power Dissipation (TA = +70C) 100-Pin TQFP 14mm x 14mm x 1mm (derated 47.6mW/C above +70C)........................3809.5mW Operating Temperature Range ...........................-40C to +85C Maximum Junction Temperature .....................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AVDD = 1.8V, OVDD = 1.8V, CVDD = 3.3V, GND = 0, external VREFIO = 1.24V, CREFIO to GND = 0.1F, CREFP to GND = 10F, CREFN to GND = 10F, fCLK = 50MHz (50% duty cycle), VDT = 0, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER DC ACCURACY (Note 2) Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error ANALOG INPUTS (IN_P, IN_N) Input Differential Range Common-Mode Voltage Range Common-Mode Voltage Range Tolerance Differential Input Impedance Differential Input Capacitance CONVERSION RATE Maximum Conversion Rate Minimum Conversion Rate Data Latency DYNAMIC CHARACTERISTICS (differential inputs, 4096-point FFT) (Note 2) Signal-to-Noise Ratio Signal-to-Noise and Distortion (First 4 Harmonics) Effective Number of Bits Spurious-Free Dynamic Range SNR SINAD ENOB SFDR fIN = 5.3MHz at -0.5dBFS fIN = 19.3MHz at -0.5dBFS fIN = 5.3MHz at -0.5dBFS fIN = 19.3MHz at -0.5dBFS fIN = 5.3MHz at -0.5dBFS fIN = 19.3MHz at -0.5dBFS fIN = 5.3MHz at -0.5dBFS fIN = 19.3MHz at -0.5dBFS 79 66.5 66.5 69.9 69.7 69.9 69.7 11.3 11.3 96 94 dB dB dB dBc fSMAX fSMIN 50 4.0 6.5 MHz MHz Cycles RIN CIN VID VCMO (Note 3) Switched capacitor load Differential input 1.4 0.76 50 2 12.5 VP-P V mV k pF -3 N INL DNL No missing codes over temperature 12 0.4 0.25 2.5 1 0.5 +2 Bits LSB LSB %FS %FS SYMBOL CONDITIONS MIN TYP MAX UNITS
2
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Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = 1.8V, OVDD = 1.8V, CVDD = 3.3V, GND = 0, external VREFIO = 1.24V, CREFIO to GND = 0.1F, CREFP to GND = 10F, CREFN to GND = 10F, fCLK = 50MHz (50% duty cycle), VDT = 0, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER Total Harmonic Distortion Intermodulation Distortion Third-Order Intermodulation Aperture Jitter Aperture Delay Small-Signal Bandwidth Full-Power Bandwidth Output Noise Over-Range Recovery Time INTERNAL REFERENCE REFADJ Internal Reference-Mode Enable Voltage REFADJ Low-Leakage Current REFIO Output Voltage Reference Temperature Coefficient EXTERNAL REFERENCE REFADJ External ReferenceMode Enable Voltage REFADJ High-Leakage Current REFIO Input Voltage REFIO Input Voltage Tolerance REFIO Input Current CMOUT Output Voltage CLOCK INPUT (CLK) Input High Voltage Input Low Voltage Clock Duty Cycle Clock Duty-Cycle Tolerance Input Leakage Input Capacitance DIIN DCIN Input at GND Input at AVDD 5 VCLKH VCLKL 50 30 5 80 0.8 x CVDD 0.2 x CVDD V V % % A pF IREFIO VCMOUT COMMON-MODE OUTPUT (CMOUT) 0.76 V (Note 4) AVDD 0.1V 200 1.24 5 <1 V A V % A VREFIO TCREFIO 1.18 (Note 4) 1.5 1.24 120 1.30 0.1 V mA V ppm/C tOR SYMBOL THD IMD IM3 tAJ tAD SSBW LSBW CONDITIONS fIN = 5.3MHz at -0.5dBFS fIN = 19.3MHz at -0.5dBFS f1 = 5.3MHz at -6.5dBFS f2 = 6.3MHz at -6.5dBFS f1 = 5.3MHz at -6.5dBFS f2 = 6.3MHz at -6.5dBFS Figure 11 Figure 11 Input at -20dBFS Input at -0.5dBFS IN_P = IN_N RS = 25, CS = 50pF MIN TYP -96 -90 90.7 98.7 <0.4 1 100 100 0.44 1 -79 MAX UNITS dBc dBc dBc psRMS ns MHz MHz LSBRMS Clock cycle
MAX1437
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3
Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs MAX1437
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = 1.8V, OVDD = 1.8V, CVDD = 3.3V, GND = 0, external VREFIO = 1.24V, CREFIO to GND = 0.1F, CREFP to GND = 10F, CREFN to GND = 10F, fCLK = 50MHz (50% duty cycle), VDT = 0, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN 0.8 x AVDD 0.2 x AVDD Input at GND Input at AVDD 5 RTERM = 100 RTERM = 100 RTERM = 100, CLOAD = 5pF RTERM = 100, CLOAD = 5pF RTERM = 100 RTERM = 100 RTERM = 100, CLOAD = 5pF RTERM = 100, CLOAD = 5pF (Note 5) 250 1.125 350 350 205 220 320 320 100 20 1.7 1.7 1.7 PD = 0 AVDD Supply Current IAVDD fIN = 19.3MHz PD = 0, DT = 1 at -0.5dBFS PD = 1, power-down, no clock input PD = 0 OVDD Supply Current IOVDD fIN = 19.3MHz PD = 0, DT = 1 at -0.5dBFS PD = 1, power-down, no clock input CVDD is used only to bias ESD-protection diodes on CLK input, Figure 2 fIN = 19.3MHz at -0.5dBFS 1.8 1.8 1.8 348 348 1.16 79 103 960 0 769 882 100 1.9 1.9 3.6 390 450 1.375 5 80 TYP MAX UNITS
DIGITAL INPUTS (PLL_, LVDSTEST, DT, SLVS, PD, T/B) Input High Threshold Input Low Threshold Input Leakage Input Capacitance Differential Output Voltage Output Common-Mode Voltage Rise Time (20% to 80%) Fall Time (80% to 20%) Differential Output Voltage Output Common-Mode Voltage Rise Time (20% to 80%) Fall Time (80% to 20%) POWER-DOWN PD Fall to Output Enable PD Rise to Output Disable POWER REQUIREMENTS AVDD Supply Voltage Range OVDD Supply Voltage Range CVDD Supply Voltage Range AVDD OVDD CVDD V V V mA mA mA A mA mW tENABLE tDISABLE ms ns VIH VIL DIIN DCIN VOHDIFF VOCM tRL tFL VOHDIFF VOCM tRS tFS V V A pF mV V ps ps mV V ps ps
LVDS OUTPUTS (OUT_P, OUT_N), SLVS/LVDS = 0
SLVS OUTPUTS (OUT_P, OUT_N, CLKOUTP, CLKOUTN, FRAMEP, FRAMEN), SLVS/LVDS = 1, DT = 1
CVDD Supply Current Power Dissipation
ICVDD PDISS
4
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Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = 1.8V, OVDD = 1.8V, CVDD = 3.3V, GND = 0, external VREFIO = 1.24V, CREFIO to GND = 0.1F, CREFP to GND = 10F, CREFN to GND = 10F, fCLK = 50MHz (50% duty cycle), VDT = 0, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN (tSAMPLE / 24) - 0.15 tSAMPLE / 12 tSAMPLE / 12 (tSAMPLE / 24) - 0.15 (tSAMPLE / 2) + 1.1 -95 0.1 0.25 (tSAMPLE / 24) + 0.15 (tSAMPLE / 2) + 2.6 TYP MAX (tSAMPLE / 24) + 0.15 UNITS
MAX1437
TIMING CHARACTERISTICS (Note 6) Data Valid to CLKOUT Rise/Fall tOD Figure 5 (Note 7) ns
CLKOUT Output-Width High CLKOUT Output-Width Low
tCH tCL
Figure 5 Figure 5
ns ns
FRAME Rise to CLKOUT Rise
tCF
Figure 4 (Note 7)
ns
Sample CLK Rise to FRAME Rise Crosstalk Gain Matching Phase Matching
tSF
Figure 4 (Note 7) (Note 2)
ns dB dB Degrees
CGM CPM
fIN = 5.3MHz (Note 2) fIN = 5.3MHz (Note 2)
Note 1: Specifications at TA +25C are guaranteed by production testing. Specifications at TA < +25C are guaranteed by design and characterization and not subject to production testing. Note 2: See definition in the Parameter Definition section at the end of this data sheet. Note 3: See the Common-Mode Output (CMOUT) section. Note 4: Connect REFADJ to GND directly to enable internal reference mode. Connect REFADJ to AVDD directly to disable the internal bandgap reference and enable external reference mode. Note 5: Measured using CREFP to GND = 1F and CREFN to GND = 1F. tENABLE time may be lowered by using smaller capacitor values. Note 6: Data valid to CLKOUT rise/fall timing is measured from 50% of data output level to 50% of clock output level. Note 7: Guaranteed by design and characterization. Not subject to production testing.
Typical Operating Characteristics
(AVDD = 1.8V, OVDD = 1.8V, CVDD = 3.3V, GND = 0, internal reference, differential input at -0.5dBFS, fIN = 5.3MHz, fCLK = 50MHz (50% duty cycle), VDT = 0, CLOAD = 10pF, TA = +25C, unless otherwise noted.)
FFT PLOT (16,384-POINT DATA RECORD)
MAX1437 toc01
FFT PLOT (16,384-POINT DATA RECORD)
MAX1437 toc02
CROSSTALK (16,384-POINT DATA RECORD)
-10 -20 AMPLITUDE (dBFS) -30 -40 -50 -60 -70 -80 -90 -100 -110 fIN(IN2) MEASURED ON CHANNEL 1, WITH INTERFERING SIGNAL ON CHANNEL 2 fIN(IN1) = 5.304814MHz fIN(IN2) = 24.0997118MHz CROSSTALK = 103dB
MAX1437 toc03
0 -10 -20 AMPLITUDE (dBFS) -30 -40 -50 -60 -70 -80 -90 -100 -110 0 5 10 15 20 HD2 HD3 fCLK = 50.1523789MHz fIN = 5.304814MHz AIN = -0.5dBFS SNR = 69.959dB SINAD = 69.950dB THD = -96.635dBc SFDR = 96.503dBc
0 -10 -20 AMPLITUDE (dBFS) -30 -40 -50 -60 -70 -80 -90 -100 -110 HD2 HD3 fCLK = 50.1523789MHz fIN = 24.0997118MHz AIN = -0.5dBFS SNR = 69.707dB SINAD = 69.672dB THD = -90.672dBc SFDR = 93.694dBc
0
25
0
5
FREQUENCY (MHz)
10 15 FREQUENCY (MHz)
20
25
0
5
10
15
20
25
FREQUENCY (MHz)
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5
Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs MAX1437
Typical Operating Characteristics (continued)
(AVDD = 1.8V, OVDD = 1.8V, CVDD = 3.3V, GND = 0, internal reference, differential input at -0.5dBFS, fIN = 5.3MHz, fCLK = 50MHz (50% duty cycle), VDT = 0, CLOAD = 10pF, TA = +25C, unless otherwise noted.)
TWO-TONE INTERMODULATION DISTORTION (16,384-POINT DATA RECORD)
MAX1437 toc04
BANDWIDTH vs. ANALOG INPUT FREQUENCY
MAX1437 toc05
SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT FREQUENCY
71 70 69 SNR (dB) 68 67 66 65 64 63 62
MAX1437 toc06
0 -10 -20 AMPLITUDE (dBFS) -30 -40 -50 -60 -70 -80 -90 -100 -110 0 5 10 15 FREQUENCY (MHz) 20 fIN(IN1) = 5.299375MHz fIN(IN2) = 6.299775MHz AIN1 = -6.5dBFS AIN2 = -6.5dBFS IMD = 90.7dBc IM3 = 98.7dBc
1 0 -1 -2 -3 GAIN (dB) -4 -5 -6 -7 -8 -9 -10 FULL-POWER BANDWIDTH -0.5dBFS
SMALL-SIGNAL BANDWIDTH -20.5dBFS
72
25
1
10
100
1000
0
20
40
60 fIN (MHz)
80
100
120
ANALOG INPUT FREQUENCY (MHz)
SIGNAL-TO-NOISE PLUS DISTORTION vs. ANALOG INPUT FREQUENCY
71 70 69 THD (dBc) SINAD (dB) 68 67 66 65 64 63 62 0 20 40 60 fIN (MHz) 80 100 120
MAX1437 toc07
TOTAL HARMONIC DISTORTION vs. ANALOG INPUT FREQUENCY
MAX1437 toc08
SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT FREQUENCY
95 90 85 SFDR (dBc) 80 75 70 65 60 55
MAX1437 toc09
72
-55 -60 -65 -70 -75 -80 -85 -90 -95 -100 0 20 40 60 fIN (MHz) 80 100
100
120
0
20
40
60 fIN (MHz)
80
100
120
SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT POWER
MAX1437 toc10
SIGNAL-TO-NOISE PLUS DISTORTION vs. ANALOG INPUT POWER
MAX1437 toc11
TOTAL HARMONIC DISTORTION vs. ANALOG INPUT POWER
-60 -65 -70 THD (dBc) -75 -80 -85 -90 -95 -100 -105 fIN = 5.304814MHz
MAX1437 toc12
72 67 62
fIN = 5.304814MHz
72 67 62 SINAD (dB) 57 52 47 42 37 32
fIN = 5.304814MHz
-55
57 SNR (dB) 52 47 42 37 32 -30 -25 -20 -15 -10 -5 0 ANALOG INPUT POWER (dBFS)
-30
-25
-20
-15
-10
-5
0
-30
-25
-20
-15
-10
-5
0
ANALOG INPUT POWER (dBFS)
ANALOG INPUT POWER (dBFS)
6
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Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs
Typical Operating Characteristics (continued)
(AVDD = 1.8V, OVDD = 1.8V, CVDD = 3.3V, GND = 0, internal reference, differential input at -0.5dBFS, fIN = 5.3MHz, fCLK = 50MHz (50% duty cycle), VDT = 0, CLOAD = 10pF, TA = +25C, unless otherwise noted.)
SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT POWER
MAX1437 toc13
MAX1437
SIGNAL-TO-NOISE RATIO vs. SAMPLING RATE
MAX1437 toc14
SIGNAL-TO-NOISE PLUS DISTORTION vs. SAMPLING RATE
71 70 69 SINAD (dB) 68 67 66 65 64 63 62 fIN = 5.304814MHz
MAX1437 toc15
105 100 95 90 SFDR (dBc)
fIN = 5.304814MHz
72 71 70 69 SNR (dB) 68 67 66 65 64 63 62
fIN = 5.304814MHz
72
85 80 75 70 65 60 55 -30 -25 -20 -15 -10 -5 0 ANALOG INPUT POWER (dBFS)
10
15
20
25
30
35
40
45
50
10
15
20
25
30
35
40
45
50
fCLK (MHz)
fCLK (MHz)
TOTAL HARMONIC DISTORTION vs. SAMPLING RATE
MAX1437 toc16
SPURIOUS-FREE DYNAMIC RANGE vs. SAMPLING RATE
MAX1437 toc17
SIGNAL-TO-NOISE RATIO vs. DUTY CYCLE
fIN = 5.304814MHz 72 71
MAX1437 toc18
-75 fIN = 5.304814MHz -80 -85
105 fIN = 5.304814MHz 100 95 SFDR (dBc) 90 85 80
73
THD (dBc)
70 SNR (dB) 10 15 20 25 30 35 40 45 50 69 68 67
-90 -95 -100 -105 10 15 20 25 30 35 40 45 50 fCLK (MHz)
66 75 fCLK (MHz) 65 30 35 40 45 50 55 60 65 70 DUTY CYCLE (%)
SIGNAL-TO-NOISE PLUS DISTORTION vs. DUTY CYCLE
MAX1437 toc19
TOTAL HARMONIC DISTORTION vs. DUTY CYCLE
MAX1437 toc20
SPURIOUS-FREE DYNAMIC RANGE vs. DUTY CYCLE
fIN = 5.304814MHz
MAX1437 toc21
73 72 71
fIN = 5.304814MHz
-75 -80 -85
fIN = 5.304814MHz
100 95 90 SFDR (dBc) 85 80 75 70
SINAD (dB)
69 68 67 66 65 30 35 40 45 50 55 60 65 70 DUTY CYCLE (%)
THD (dBc)
70
-90 -95 -100 -105 30 35 40 45 50 55 60 65 70 DUTY CYCLE (%)
30
35
40
45
50
55
60
65
70
DUTY CYCLE (%)
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7
Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs MAX1437
Typical Operating Characteristics (continued)
(AVDD = 1.8V, OVDD = 1.8V, CVDD = 3.3V, GND = 0, internal reference, differential input at -0.5dBFS, fIN = 5.3MHz, fCLK = 50MHz (50% duty cycle), VDT = 0, CLOAD = 10pF, TA = +25C, unless otherwise noted.)
SIGNAL-TO-NOISE RATIO vs. TEMPERATURE
MAX1437 toc22
SIGNAL-TO-NOISE PLUS DISTORTION vs. TEMPERATURE
MAX1437 toc23
TOTAL HARMONIC DISTORTION vs. TEMPERATURE
-91 -92 -93
MAX1437 toc24
73 72 71
fCLK = 50MHz fIN = 19.8MHz 4096-POINT DATA RECORD
73 72 71 SINAD (dB) 70 69 68 67 66 65
fCLK = 50MHz fIN = 19.8MHz 4096-POINT DATA RECORD
-90
70 SNR (dB) 69 68 67 66 65 -40 -15 10 35 60 85 TEMPERATURE (C)
THD (dBc)
-94 -95 -96 -97 -98 -99 -100 fCLK = 50MHz fIN = 19.8MHz 4096-POINT DATA RECORD -40 -15 10 35 60 85
-40
-15
10
35
60
85
TEMPERATURE (C)
TEMPERATURE (C)
SPURIOUS-FREE DYNAMIC RANGE vs. TEMPERATURE
MAX1437 toc25
MAX1437 toc26
94 93 92 SFDR (dBc)
fCLK = 50MHz fIN = 19.8MHz 4096-POINT DATA RECORD
350 340 IAVDD (mA)
80 75 IOVDD (mA) 70 65 60 55
91 90 89 88 87 86 85 -40 -15 10 35 60 85 TEMPERATURE (C)
330 320 310 300 290 280 0 10 20 30 40 50 fCLK (MHz)
0
10
20
30
40
50
fCLK (MHz)
OFFSET ERROR vs. TEMPERATURE
MAX1437 toc28
GAIN ERROR vs. TEMPERATURE
MAX1437 toc29
INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE
0.4 0.3 0.2 INL (LSB) 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5
MAX1437 toc30
0.04 0.03 OFFSET ERROR (%FS) 0.02 0.01 0 -0.01 -0.02 -0.03 -0.04 -40 -15 10 35 60
0.6 0.4 0.2 GAIN ERROR (%FS) 0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4
0.5
85
-40
-15
10
35
60
85
0
512 1024 1536 2048 2560 3072 3584 4096 DIGITAL OUTPUT CODE
TEMPERATURE (C)
TEMPERATURE (C)
8
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MAX1437 toc27
95
360
SUPPLY CURRENT vs. SAMPLING RATE (AVDD)
85
SUPPLY CURRENT vs. SAMPLING RATE (0VDD)
Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs
Typical Operating Characteristics (continued)
(AVDD = 1.8V, OVDD = 1.8V, CVDD = 3.3V, GND = 0, internal reference, differential input at -0.5dBFS, fIN = 5.3MHz, fCLK = 50MHz (50% duty cycle), VDT = 0, CLOAD = 10pF, TA = +25C, unless otherwise noted.)
DIFFERENTIAL NONLINEARITY vs. DIGITAL OUTPUT CODE
MAX1437 toc31
MAX1437
INTERNAL REFERENCE VOLTAGE vs. SUPPLY VOLTAGE
MAX1437 toc32
INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE
AVDD = OVDD
MAX1437 toc33
0.3 0.2 0.1 DNL (LSB)
1.2510
AVDD = OVDD
1.26
1.2500 VREFIO (V) VREFIO (V) 1.7 1.8 1.9 2.0 2.1
1.25
0 -0.1
1.2490
1.24
1.2480 -0.2 -0.3 0 512 1024 1536 2048 2560 3072 3584 4096 DIGITAL OUTPUT CODE 1.2470 SUPPLY VOLTAGE (V)
1.23
1.22 -40 -15 10 35 60 85 TEMPERATURE (C)
INTERNAL REFERENCE VOLTAGE vs. REFERENCE LOAD CURRENT
MAX1437 toc34
CMOUT VOLTAGE vs. SUPPLY VOLTAGE
MAX1437 toc35
CMOUT VOLTAGE vs. TEMPERATURE
AVDD = OVDD
MAX1437 toc36
1.40 1.35 1.30
0.770
AVDD = OVDD
0.770
0.768
0.768
VCMOUT (V)
1.20 1.15 1.10 1.05 1.00 -350 -250 -150 -50 50 150 250 350 IREFIO (A)
VCMOUT (V)
1.25 VREFIO (V)
0.766 0.764
0.766
0.764
0.762
0.762
0.760 1.7 1.8 1.9 2.0 2.1 SUPPLY VOLTAGE (V)
0.760 -40
-15
10
35
60
85
TEMPERATURE (C)
CMOUT VOLTAGE vs. LOAD CURRENT
1.6 1.4 1.2 VCMOUT (V) 1.0 0.8 0.6 0.4 0.2 0 0 500 1000 ICMOUT (A) 1500 2000
MAX1437 toc37
1.8
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9
Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs MAX1437
Pin Description
PIN 1, 4, 7, 10, 16, 19, 22, 25, 26, 27, 30, 36, 89, 92, 96, 99, 100 2 3 5 6 8 9 11, 12, 13, 15, 37-42, 86, 87, 88 14, 31, 50, 51, 70, 75, 76 17 18 20 21 23 24 28 29 32 33 NAME GND IN1P IN1N IN2P IN2N IN3P IN3N AVDD FUNCTION Ground. Connect all GND pins to the same potential. Channel 1 Positive Analog Input Channel 1 Negative Analog Input Channel 2 Positive Analog Input Channel 2 Negative Analog Input Channel 3 Positive Analog Input Channel 3 Negative Analog Input Analog Power Input. Connect AVDD to a +1.7V to +1.9V power supply. Bypass AVDD to GND with a 0.1F capacitor as close to the device as possible. Bypass the AVDD power plane to the GND plane with a bulk 2.2F capacitor. Connect all AVDD pins to the same potential. No Connection. Not internally connected. Channel 4 Positive Analog Input Channel 4 Negative Analog Input Channel 5 Positive Analog Input Channel 5 Negative Analog Input Channel 6 Positive Analog Input Channel 6 Negative Analog Input Channel 7 Positive Analog Input Channel 7 Negative Analog Input Double-Termination Select. Drive DT high to select the internal 100 termination between the differential output pairs. Drive DT low to select no output termination. Differential Output-Signal Format-Select Input. Drive SLVS/LVDS high to select SLVS outputs. Drive SLVS/LVDS low to select LVDS outputs. Clock Power Input. Connect CVDD to a +1.7V to +3.6V supply. Bypass CVDD to GND with a 0.1F capacitor in parallel with a 2.2F capacitor. Install the bypass capacitors as close to the device as possible. Single-Ended CMOS Clock Input Output-Driver Power Input. Connect OVDD to a +1.7V to +1.9V power supply. Bypass OVDD to GND with a 0.1F capacitor as close to the device as possible. Bypass the OVDD power plane to the GND plane with a bulk 2.2F capacitor. Connect all OVDD pins to the same potential. Channel 7 Negative LVDS/SLVS Output Channel 7 Positive LVDS/SLVS Output Channel 6 Negative LVDS/SLVS Output Channel 6 Positive LVDS/SLVS Output Channel 5 Negative LVDS/SLVS Output Channel 5 Positive LVDS/SLVS Output Channel 4 Negative LVDS/SLVS Output Channel 4 Positive LVDS/SLVS Output
N.C. IN4P IN4N IN5P IN5N IN6P IN6N IN7P IN7N DT SLVS/LVDS
34 35 43, 46, 49, 54, 57, 60, 63, 64, 67, 71, 74, 77 44 45 47 48 52 53 55 56
CVDD CLK OVDD OUT7N OUT7P OUT6N OUT6P OUT5N OUT5P OUT4N OUT4P
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Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs
Pin Description (continued)
PIN 58 59 61 62 65 66 68 69 72 73 78 79 80 NAME FRAMEN FRAMEP CLKOUTN CLKOUTP OUT3N OUT3P OUT2N OUT2P OUT1N OUT1P OUT0N OUT0P LVDSTEST FUNCTION Negative Frame-Alignment LVDS/SLVS Output. A rising edge on the differential FRAME output aligns to a valid D0 in the output data stream. Positive Frame-Alignment LVDS/SLVS Output. A rising edge on the differential FRAME output aligns to a valid D0 in the output data stream. Negative LVDS/SLVS Serial Clock Output Positive LVDS/SLVS Serial Clock Output Channel 3 Negative LVDS/SLVS Output Channel 3 Positive LVDS/SLVS Output Channel 2 Negative LVDS/SLVS Output Channel 2 Positive LVDS/SLVS Output Channel 1 Negative LVDS/SLVS Output Channel 1 Positive LVDS/SLVS Output Channel 0 Negative LVDS/SLVS Output Channel 0 Positive LVDS/SLVS Output LVDS Test Pattern Enable. Drive LVDSTEST high to enable the output test pattern (0000 1011 1101 MSB LSB). As with the analog conversion results, the test pattern data is output LSB first. Drive LVDSTEST low for normal operation. Power-Down Input. Drive PD high to power down all channels and reference. Drive PD low for normal operation. PLL Control Input 3. See Table 1 for details. PLL Control Input 2. See Table 1 for details. PLL Control Input 1. See Table 1 for details. Output Format-Select Input. Drive T/B high to select binary output format. Drive T/B low to select two's-complement output format. Negative Reference Bypass Output. Connect a 1F (10F typ) capacitor between REFP and REFN, and connect a 1F (10F typ) capacitor between REFN and GND. Place the capacitors as close to the device as possible on the same side of the printed circuit (PC) board. Positive Reference Bypass Output. Connect a 1F (10F typ) capacitor between REFP and REFN, and connect a 1F (10F typ) capacitor between REFP and GND. Place the capacitors as close to the device as possible on the same side of the PC board. Reference Input/Output. For internal reference operation (REFADJ = GND), the reference output voltage is 1.24V. For external reference operation (REFADJ = AVDD), apply a stable reference voltage at REFIO. Bypass to GND with 0.1F. Internal/External Reference-Mode-Select and Reference Adjust Input. For internal reference mode, connect REFADJ directly to GND. For external reference mode, connect REFADJ directly to AVDD. For reference-adjust mode, see the Full-Scale Range Adjustments Using the Internal Reference section. Common-Mode Reference Voltage Output. CMOUT outputs the input common-mode voltage for DC-coupled applications. Bypass CMOUT to GND with 0.1F capacitor. Channel 0 Positive Analog Input Channel 0 Negative Analog Input Exposed Paddle. EP is internally connected to GND. Connect EP to GND.
MAX1437
81 82 83 84 85
PD PLL3 PLL2 PLL1 T/B
90
REFN
91
REFP
93
REFIO
94
REFADJ
95 97 98 --
CMOUT IN0P IN0N EP
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Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs MAX1437
Functional Diagram
REFADJ REFIO REFP REFN PD AVDD OVDD DT SLVS/LVDS
CMOUT ICMV* IN0P T/H IN0N
REFERENCE SYSTEM
POWER CONTROL
MAX1437
OUTPUT CONTROL
LVDSTEST T/B
12-BIT PIPELINE ADC
12:1 SERIALIZER
OUT0P OUT0N
IN1P T/H IN1N
12-BIT PIPELINE ADC
12:1 SERIALIZER
OUT1P OUT1N
LVDS/SLVS OUTPUT DRIVERS IN7P IN7N T/H 12-BIT PIPELINE ADC 12:1 SERIALIZER OUT7P OUT7N FRAMEP FRAMEN CLOCK CIRCUITRY PLL 6x CLKOUTP CLKOUTN
CLK
CVDD
PLL1
PLL2
PLL3
GND
*ICMV = INPUT COMMON-MODE VOLTAGE (INTERNALLY GENERATED).
Detailed Description
The MAX1437 ADC features fully differential inputs, a pipelined architecture, and digital error correction for high-speed signal conversion. The ADC pipeline architecture moves the samples taken at the inputs through the pipeline stages every half clock cycle. The converted digital results are serialized and sent through the LVDS/SLVS output drivers. The total clock-cycle latency from input to output is 6.5 clock cycles. The MAX1437 offers eight separate fully differential channels with synchronized inputs and outputs. Configure the outputs for binary or two's complement with the T/B digital input. Global power-down minimizes power consumption.
Input Circuit
Figure 1 displays a simplified diagram of the input T/H circuits. In track mode, switches S1, S2a, S2b, S4a, S4b, S5a, and S5b are closed. The fully differential circuits sample the input signals onto the two capacitors (C2a and C2b) through switches S4a and S4b. S2a and S2b set the common mode for the operational transconductance amplifier (OTA), and open simultaneously with S1, sampling the input waveform. Switches S4a, S4b, S5a, and S5b are then opened before switches S3a and S3b connect capacitors C1a and C1b to the output of the amplifier and switch S4c is closed. The resulting differential voltages are held on capacitors C2a and C2b. The amplifiers charge capacitors C1a and C1b to the same values originally held on C2a and C2b. These values are
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Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs MAX1437
SWITCHES SHOWN IN TRACK MODE INTERNALLY GENERATED COMMON-MODE LEVEL*
INTERNAL COMMON-MODE BIAS* AVDD
INTERNAL BIAS*
MAX1437
S2a C1a
S5a
S3a S4a IN_P OUT S4c IN_N S4b C2b C1b S3b GND S2b INTERNAL COMMON-MODE BIAS* S5b S1 OTA OUT C2a
INTERNAL BIAS*
INTERNALLY GENERATED COMMON-MODE LEVEL*
*NOT EXTERNALLY ACCESSIBLE
Figure 1. Internal Input Circuit
then presented to the first-stage quantizers and isolate the pipelines from the fast-changing inputs. Analog inputs, IN_P to IN_N, are driven differentially. For differential inputs, balance the input impedance of IN_P and IN_N for optimum performance.
Reference Configurations (REFIO, REFADJ, REFP, and REFN)
The MAX1437 provides an internal 1.24V bandgap reference or can be driven with an external reference voltage. The full-scale analog differential input range is FSR. FSR (full-scale range) is given by the following equation: FSR = (0.700 x VREFIO ) 1.24V
where VREFIO is the voltage at REFIO, generated internally or externally. For a VREFIO = 1.24V, the full-scale input range is 700mV (1.4VP-P).
Internal Reference Mode Connect REFADJ to GND to use the internal bandgap reference directly. The internal bandgap reference generates VREFIO to be 1.24V with a 120ppm/C temperature coefficient in internal reference mode. Connect an external 0.1F bypass capacitor from REFIO to GND for stability. REFIO sources up to 200A and sinks up to 200A for external circuits, and REFIO has a 75mV/mA load regulation. REFIO has >1M to GND when the MAX1437 is in power-down mode. The internal reference circuit requires 100ms (CREFP to GND = CREFN to GND = 1F) to power up and settle when power is applied to the MAX1437 or when PD transitions from high to low. To compensate for gain errors or to decrease or increase the ADC's FSR, add an external resistor between REFADJ and GND or REFADJ and REFIO. This adjusts the internal reference value of the MAX1437 by up to 5% of its nominal value. See the Full-Scale Range Adjustments Using the Internal Reference section.
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Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs MAX1437
Connect 1F (10F typ) capacitors to GND from REFP and REFN and a 1F (10F typ) capacitor between REFP and REFN as close to the device as possible on the same side of the PC board. External Reference Mode The external reference mode allows for more control over the MAX1437 reference voltage and allows multiple converters to use a common reference. Connect REFADJ to AV DD to disable the internal reference. Apply a stable 1.18V to 1.30V source at REFIO. Bypass REFIO to GND with a 0.1F capacitor. The REFIO input impedance is >1M.
Table 1. PLL1, PLL2, and PLL3 Configuration Table
PLL1 0 0 0 0 1 1 1 1 PLL2 0 0 1 1 0 0 1 1 PLL3 0 1 0 1 0 1 0 1 INPUT CLOCK RANGE (MHz) MIN 45.0 32.5 22.5 16.3 11.3 8.1 5.6 4.0 MAX 50.0 45.0 32.5 22.5 16.3 11.3 8.1 5.6
Clock Input (CLK)
The MAX1437 accepts a CMOS-compatible clock signal with a wide 20% to 80% input clock duty cycle. Drive CLK with an external single-ended clock signal. Figure 2 shows the simplified clock input diagram. Low clock jitter is required for the specified SNR performance of the MAX1437. Analog input sampling occurs on the rising edge of CLK, requiring this edge to provide the lowest possible jitter. Jitter limits the maximum SNR performance of any ADC according to the following relationship: 1 SNR = 20 x log 2 x x fIN x t J where fIN represents the analog input frequency and tJ is the total system clock jitter. PLL Inputs (PLL1, PLL2, PLL3) The MAX1437 features a PLL that generates an output clock signal with 6 times the frequency of the input clock. The output clock signal is used to clock data out of the MAX1437 (see the System Timing Requirements
section). Set the PLL1, PLL2, and PLL3 bits according to the input clock range provided in Table 1.
System Timing Requirements
Figure 3 shows the relationship between the analog inputs, input clock, frame-alignment output, serial-clock output, and serial-data output. The differential analog input (IN_P and IN_N) is sampled on the rising edge of the CLK signal and the resulting data appears at the digital outputs 6.5 clock cycles later. Figure 4 provides a detailed, two-conversion timing diagram of the relationship between the inputs and the outputs. Clock Output (CLKOUTP, CLKOUTN) The MAX1437 provides a differential clock output that consists of CLKOUTP and CLKOUTN. As shown in Figure 4, the serial output data is clocked out of the MAX1437 on both edges of the clock output. The frequency of the output clock is six times the frequency of CLK. Frame-Alignment Output (FRAMEP, FRAMEN) The MAX1437 provides a differential frame-alignment signal that consists of FRAMEP and FRAMEN. As shown in Figure 4, the rising edge of the frame-alignment signal corresponds to the first bit (D0) of the 12bit serial data stream. The frequency of the framealignment signal is identical to the frequency of the input clock. Serial Output Data (OUT_P, OUT_N) The MAX1437 provides its conversion results through individual differential outputs consisting of OUT_P and OUT_N. The results are valid 6.5 input clock cycles after the sample is taken. As shown in Figure 3, the output data is clocked out on both edges of the output clock, LSB (D0) first. Figure 5 provides the detailed serial-output timing diagram.
AVDD
MAX1437
CVDD CLK GND DUTY-CYCLE EQUALIZER
Figure 2. Clock Input Circuitry
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Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs MAX1437
N+2 N (VIN_P VIN_N) N+1 tSAMPLE N+3 N+5 N+4 N+7 N+6 N+8 N+9
CLK
6.5 CLOCK-CYCLE DATA LATENCY
(VFRAMEP VFRAMEN)*
(VCLKOUTP VCLKOUTN)
(VOUT_P VOUT_N) OUTPUT DATA FOR SAMPLE N-6 *DUTY CYCLE VARIES DEPENDING ON INPUT CLOCK FREQUENCY. OUTPUT DATA FOR SAMPLE N
Figure 3. Global Timing Diagram
N+2 N (VIN_P - VIN_N) tSAMPLE CLK (VFRAMEP VFRAMEN)* (VCLKOUTP VCLKOUTN) (VOUT_P VOUT_N) D5N-7 D6N-7 D7N-7 D8N-7 D9N-7 D10N-7 D11N-7 D0N-6 D1N-6 D2N-6 D3N-6 D4N-6 D5N-6 D6N-6 D7N-6 D8N-6 D9N-6 D10N-6 D11N-6 D0N-5 D1N-5 D2N-5 D3N-5 D4N-5 D5N-5 D6N-5 *DUTY CYCLE DEPENDS ON INPUT CLOCK FREQUENCY. N+1 tSF
tCF
Figure 4. Detailed Two-Conversion Timing Diagram
tCH (VCLKOUTP VCLKOUTN) (VOUT_P VOUT_N)
tCL
tOD D0 D1 D2
tOD D3
Figure 5. Serialized-Output Detailed Timing Diagram ______________________________________________________________________________________ 15
Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs MAX1437
Table 2. Output Code Table (VREFIO = 1.24V)
TWO'S-COMPLEMENT DIGITAL OUTPUT CODE (T/B = 0) BINARY D11 D0 0111 1111 1111 0111 1111 1110 0000 0000 0001 0000 0000 0000 1111 1111 1111 1000 0000 0001 1000 0000 0000 HEXADECIMAL EQUIVALENT OF D11 D0 0x7FF 0x7FE 0x001 0x000 0xFFF 0x801 0x800 DECIMAL EQUIVALENT OF D11 D0 +2047 +2046 +1 0 -1 -2047 -2048 OFFSET BINARY DIGITAL OUTPUT CODE (T/B = 1) BINARY D11 D0 1111 1111 1111 1111 1111 1110 1000 0000 0001 1000 0000 0000 0111 1111 1111 0000 0000 0001 0000 0000 0000 HEXADECIMAL EQUIVALENT OF D11 D0 0xFFF 0xFFE 0x801 0x800 0x7FF 0x001 0x000 DECIMAL EQUIVALENT OF D11 D0 +4095 +4094 +2049 +2048 +2047 +1 0 VIN_P - VIN_N (mV) (VREFIO = 1.24V)
+699.66 +699.32 +0.34 0 -0.34 -699.66 -700.00
1 LSB = 2 x FSR 4096 FSR TWO'S-COMPLEMENT OUTPUT CODE (LSB) 0x7FF 0x7FE 0x7FD
FSR = 700mV x VREFIO 1.24V FSR OFFSET BINARY OUTPUT CODE (LSB) 0xFFF 0xFFE 0xFFD
1 LSB = 2 x FSR 4096 FSR
FSR = 700mV x VREFIO 1.24V FSR
0x001 0x000 0xFFF
0x801 0x800 0x7FF
0x803 0x802 0x801 0x800 -2047 -2045 -1 0 +1 +2045 +2047
0x003 0x002 0x800 0x000 -2047 -2045 -1 0 +1 +2045 +2047 DIFFERENTIAL INPUT VOLTAGE (LSB)
DIFFERENTIAL INPUT VOLTAGE (LSB)
Figure 6. Two's-Complement Transfer Function (T/B = 0)
Figure 7. Binary Transfer Function (T/B = 1)
Output Data Format (T/B) Transfer Functions The MAX1437 output data format is either offset binary or two's complement, depending on the logic-input T/B. With T/B low, the output data format is two's complement. With T/B high, the output data format is offset binary. The following equations, Table 2, and Figures 6 and 7 define the relationship between the digital output and the analog input. For two's complement (T/B = 0): VIN _ P - VIN _ N = FSR x 2 x CODE10 4096
and for offset binary (T/B = 1): VIN _ P - VIN _ N = FSR x 2 x CODE10 - 2048 4096
where CODE10 is the decimal equivalent of the digital output code as shown in Table 2. Keep the capacitive load on the MAX1437 digital outputs as low as possible.
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Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs
LVDS and SLVS Signals (SLVS/LVDS)
Drive SLVS/LVDS low for LVDS or drive SLVS/LVDS high for SLVS levels at the MAX1437 outputs (OUT_P, OUT_N, CLKOUTP, CLKOUTN, FRAMEP, and FRAMEN). For SLVS levels, enable double-termination by driving DT high. See the Electrical Characteristics table for LVDS and SLVS output voltage levels.
DT
MAX1437
OUT_P/ CLKOUTP/ FRAMEP
Z0 = 50
LVDS Test Pattern (LVDSTEST)
Drive LVDSTEST high to enable the output test pattern on all LVDS or SLVS output channels. The output test pattern is 0000 1011 1101. Drive LVDSTEST low for normal operation (test pattern disabled).
100 100
Common-Mode Output (CMOUT)
CMOUT provides a common-mode reference for DCcoupled analog inputs. If the input is DC-coupled, match the output common-mode voltage of the circuit driving the MAX1437 to the output voltage at VCMOUT to within 50mV. It is recommended that the output common-mode voltage of the driving circuit be derived from CMOUT.
MAX1437
OUT_N/ CLKOUTN/ FRAMEN Z0 = 50
SWITCHES ARE CLOSED WHEN DT IS HIGH. SWITCHES ARE OPEN WHEN DT IS LOW.
Double-Termination (DT)
The MAX1437 offers an optional, internal 100 termination between the differential output pairs (OUT_P and OUT_N, CLKOUTP and CLKOUTN, FRAMEP and FRAMEN). In addition to the termination at the end of the line, a second termination directly at the outputs helps eliminate unwanted reflections down the line. This feature is useful in applications where trace lengths are long (>5in) or with mismatched impedance. Drive DT high to select doubletermination, or drive DT low to disconnect the internal termination resistor (single-termination). Selecting double-termination increases the OVDD supply current (see Figure 8).
Figure 8. Double-Termination
*
OUT_P, OUT_N, CLKOUTP, CLKOUTN, FRAMEP, and FRAMEN have approximately 342 between the output pairs when DT is low. When DT is high, the differential output pairs have 100 between each pair.
When operating from the internal reference, the wakeup time from power-down is typically 100ms (CREFP to GND = CREFN to GND = 1F). When using an external reference, the wake-up time is dependent on the external reference drivers.
Power-Down Mode (PD)
The MAX1437 offers a power-down mode to efficiently use power by transitioning to a low-power state when conversions are not required. PD controls the power-down mode of all channels and the internal reference circuitry. Drive PD high to enable power-down. In power-down mode, the output impedance of all of the LVDS/SLVS outputs is approximately 342, if DT is low. The output impedance of the differential LVDS/SLVS outputs is 100 when DT is high. See the Electrical Characteristics table for typical supply currents during power-down. The following list shows the state of the analog inputs and digital outputs in power-down mode: * * IN_P, IN_N analog inputs are disconnected from the internal input amplifier REFIO has >1M to GND
Applications Information
Full-Scale Range Adjustments Using the Internal Reference
The MAX1437 supports a full-scale adjustment range of 10% (5%). To decrease the full-scale range, add a 25k to 250k external resistor or potentiometer (RADJ) between REFADJ and GND. To increase the full-scale range, add a 25k to 250k resistor between REFADJ and REFIO. Figure 9 shows the two possible configurations. The following equations provide the relationship between RADJ and the change in the analog full-scale range: 1.25k FSR = 0.7V 1 + RADJ for RADJ connected between REFADJ and REFIO, and:
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Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs MAX1437
ADC FULL-SCALE = REFT - REFB REFERENCESCALING AMPLIFIER VIN N.C. 10 0.1F 1 T1 2 5 0.1F 3 4 MINICIRCUITS ADT1-1WT 25k TO 250k 6 39pF IN_P
REFT REFB REFERENCE BUFFER
G
MAX1437
REFIO 1V REFADJ CONTROL LINE TO DISABLE REFERENCE BUFFER
0.1F
10 IN_N 39pF
Figure 10. Transformer-Coupled Input Drive
25k TO 250k
CVDD to GND with a 0.1F ceramic capacitor in parallel with a 2.2F ceramic capacitor.
MAX1437
AVCC AVCC / 2
Figure 9. Circuit Suggestions to Adjust the ADC's Full-Scale Range
1.25k FSR = 0.7V 1 - RADJ for RADJ connected between REFADJ and GND.
Using Transformer Coupling
An RF transformer (Figure 10) provides an excellent solution to convert a single-ended input source signal to a fully differential signal. The MAX1437 input common-mode voltage is internally biased to 0.76V (typ) with f CLK = 50MHz. Although a 1:1 transformer is shown, a step-up transformer can be selected to reduce the drive requirements. A reduced signal swing from the input driver, such as an op amp, can also improve the overall distortion.
Multilayer boards with ample ground and power planes produce the highest level of signal integrity. Connect MAX1437 ground pins and the exposed backside paddle to the same ground plane. The MAX1437 relies on the exposed-backside-paddle connection for a lowinductance ground connection. Isolate the ground plane from any noisy digital system ground planes. Route high-speed digital signal traces away from the sensitive analog traces. Keep all signal lines short and free of 90 turns. Ensure that the differential analog input network layout is symmetric and that all parasitics are balanced equally. Refer to the MAX1434/MAX1436/MAX1437/MAX1438 EV kit data sheet for an example of symmetric input layout.
Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. For the MAX1437, this straight line is between the end points of the transfer function, once offset and gain errors have been nullified. INL deviations are measured at every step and the worst-case deviation is reported in the Electrical Characteristics table.
Grounding, Bypassing, and Board Layout
The MAX1437 requires high-speed board layout design techniques. Refer to the MAX1434/MAX1436/MAX1437/ MAX1438 EV kit data sheet for a board layout reference. Locate all bypass capacitors as close to the device as possible, preferably on the same side as the ADC, using surface-mount devices for minimum inductance. Bypass AV DD to GND with a 0.1F ceramic capacitor in parallel with a 0.1F ceramic capacitor. Bypass OVDD to GND with a 0.1F ceramic capacitor in parallel with a 2.2F ceramic capacitor. Bypass
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Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between an actual step width and the ideal value of 1 LSB. A DNL error specification of less than 1 LSB guarantees no missing codes and a monotonic transfer function. For the MAX1437, DNL deviations are measured at every step and the worst-case deviation is reported in the Electrical Characteristics table.
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Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs
Offset Error
Offset error is a figure of merit that indicates how well the actual transfer function matches the ideal transfer function at a single point. For the MAX1437, the ideal midscale digital output transition occurs when there is 1/2 LSBs across the analog inputs (Figures 6 and 7). Bipolar offset error is the amount of deviation between the measured midscale transition point and the ideal midscale transition point.
CLK tAD ANALOG INPUT tAJ SAMPLED DATA
MAX1437
Gain Error
Gain error is a figure of merit that indicates how well the slope of the actual transfer function matches the slope of the ideal transfer function. For the MAX1437, the gain error is the difference of the measured full-scale and zero-scale transition points minus the difference of the ideal full-scale and zero-scale transition points. For the bipolar devices (MAX1437), the full-scale transition point is from 0x7FE to 0x7FF for two's-complement output format (0xFFE to 0xFFF for offset binary) and the zero-scale transition point is from 0x800 to 0x801 for two's complement (0x000 to 0x001 for offset binary).
T/H HOLD TRACK HOLD
Figure 11. Aperture Jitter/Delay Specifications
For the MAX1437, SNR is computed by taking the ratio of the RMS signal to the RMS noise. RMS noise includes all spectral components to the Nyquist frequency excluding the fundamental, the first six harmonics (HD2-HD7), and the DC offset.
Crosstalk
Crosstalk indicates how well each analog input is isolated from the others. For the MAX1437, a 5.3MHz, -0.5dBFS analog signal is applied to one channel while a 24.1MHz, -0.5dBFS analog signal is applied to another channel. An FFT is taken on the channel with the 5.3MHz analog signal. From this FFT, the crosstalk is measured as the difference in the 5.3MHz and 24.1MHz amplitudes.
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS signal to the RMS noise plus distortion. RMS noise plus distortion includes all spectral components to the Nyquist frequency, excluding the fundamental and the DC offset.
Effective Number of Bits (ENOB)
ENOB specifies the dynamic performance of an ADC at a specific input frequency and sampling rate. An ideal ADC's error consists of quantization noise only. ENOB for a full-scale sinusoidal input waveform is computed from: SINAD - 1.76 ENOB = 6.02
Aperture Delay
Aperture delay (tAD) is the time defined between the rising edge of the sampling clock and the instant when an actual sample is taken. See Figure 11.
Aperture Jitter
Aperture jitter (tAJ) is the sample-to-sample variation in the aperture delay. See Figure 11.
Total Harmonic Distortion (THD)
THD is the ratio of the RMS sum of the first six harmonics of the input signal to the fundamental itself. This is expressed as:
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC's resolution (N bits): SNRdB[max] = 6.02dB x N x 1.76dB In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc.
V22 + V32 + V4 2 + V52 + V62 + V72 THD = 20 x log V1

Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio expressed in decibels of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest spurious
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Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs MAX1437
component, excluding DC offset. SFDR is specified in decibels relative to the carrier (dBc).
Full-Power Bandwidth
A large -0.5dBFS analog input signal is applied to an ADC, and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by -3dB. This point is defined as fullpower input bandwidth frequency.
Intermodulation Distortion (IMD)
IMD is the total power of the IM2 to IM5 intermodulation products to the Nyquist frequency relative to the total input power of the two input tones f1 and f2. The individual input tone levels are at -6.5dBFS. The intermodulation products are as follows: * 2nd-order intermodulation products (IM2): f1 + f2, f2 - f1 * * * 3rd-order intermodulation products (IM3): 2 x f1 - f2, 2 x f2 - f1, 2 x f1 + f2, 2 x f2 + f1 4th-order intermodulation products (IM4): 3 x f1 - f2, 3 x f2 - f1, 3 x f1 + f2, 3 x f2 + f1 5th-order intermodulation products (IM5): 3 x f1 - 2 x f2, 3 x f2 - 2 x f1, 3 x f1 + 2 x f2, 3 x f2 + 2 x f1
Gain Matching
Gain matching is a figure of merit that indicates how well the gain of all eight ADC channels is matched to each other. For the MAX1437, gain matching is measured by applying the same 5.3MHz, -0.5dBFS analog signal to all analog input channels. These analog inputs are sampled at 50Msps and the maximum deviation in amplitude is reported in dB as gain matching in the Electrical Characteristics table.
Phase Matching
Phase matching is a figure of merit that indicates how well the phases of all eight ADC channels are matched to each other. For the MAX1437, phase matching is measured by applying the same 5.3MHz, -0.5dBFS analog signal to all analog input channels. These analog inputs are sampled at 50Msps and the maximum deviation in phase is reported in degrees as phase matching in the Electrical Characteristics table.
Third-Order Intermodulation (IM3)
IM3 is the total power of the 3rd-order intermodulation product to the Nyquist frequency relative to the total input power of the two input tones f1 and f2. The individual input tone levels are at -6.5dBFS. The 3rd-order intermodulation products are 2 x f1 - f2, 2 x f2 - f1, 2 x f1 + f2, 2 x f2 + f1.
Small-Signal Bandwidth
A small -20.5dBFS analog input signal is applied to an ADC so that the signal's slew rate does not limit the ADC's performance. The input frequency is then swept up to the point where the amplitude of the digitized conversion result has decreased by -3dB.
20
______________________________________________________________________________________
Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs
Pin Configuration
PLL3 PD LVDSTEST OUT0P IN0P GND CMOUT REFADJ REFIO GND REFP REFN GND AVDD AVDD AVDD T/B PLL1 PLL2 GND IN0N TOP VIEW OUT0N OVDD
MAX1437
GND
100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
N.C.
GND IN1P IN1N GND IN2P IN2N GND IN3P IN3N GND AVDD AVDD AVDD N.C. AVDD GND IN4P IN4N GND IN5P IN5N GND IN6P IN6N GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
N.C. OVDD OUT1P OUT1N OVDD N.C. OUT2P OUT2N OVDD OUT3P OUT3N OVDD OVDD CLKOUTP CLKOUTN OVDD FRAMEP FRAMEN OVDD OUT4P OUT4N OVDD OUT5P OUT5N N.C.
MAX1437
EXPOSED PADDLE--CONNECTED TO GND
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
OVDD OUT7N OUT7P OVDD OUT6N
OUT6P
AVDD
IN7N
CVDD CLK GND AVDD AVDD AVDD AVDD
SLVS/LVDS
TQFP 14mm x 14mm x 1mm
______________________________________________________________________________________
AVDD
0VDD N.C.
GND IN7P
GND N.C. DT
GND
21
Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs MAX1437
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) For the MAX1437 exposed paddle variation, the package code is C100E-2. 14x14x1.00L TQPF, EXP. PAD.EPS 22 ______________________________________________________________________________________
Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) For the MAX1437 exposed paddle variation, the package code is C100E-2.
MAX1437
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 23 (c) 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.

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